Electrical interconnect for an integrated circuit package and method of making same
US9570376B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2015 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Feb 19, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package includes a first substrate having at least one circuit layer formed on a first surface thereof, a first die mounted on a second surface of the first substrate opposite from the first surface, and an interconnection assembly comprising upper and lower conductive layers provided on an insulating substrate, with the upper conductive layer of the interconnection assembly affixed to the second surface of the first substrate and electrically connected to the at least one circuit layer of the first substrate. A second substrate is positioned on a side of the first die opposite from the first substrate so as to position the die between the first and second substrates, the second substrate having at least one circuit layer formed on an outward facing first surface thereof that is electrically connected to at least one of the lower conductive layers of the interconnection assembly and the first die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.