Semiconductor package assembly with through silicon via interconnect
US9570399B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2015 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Dec 9, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06544
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor die mounted on a base. The first semiconductor die includes a semiconductor substrate. A first array of TSV interconnects and a second array of TSV interconnects are formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. A first ground TSV interconnect is disposed within the interval region. A second semiconductor die is mounted on the first semiconductor die, having a ground pad thereon. The first ground TSV interconnect of the first semiconductor die has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.