Stacking of multiple dies for forming three dimensional integrated circuit (3DIC) structure
US9570421B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2013 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Nov 25, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/37001
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The embodiments described provide methods and structures for forming support structures between dies and substrate(s) of a three dimensional integrated circuit (3DIC) structures. Each support structure adheres to surfaces of two neighboring dies or die and substrate to relieve stress caused by bowing of the die(s) and/or substrate on the bonding structures formed between the dies or die and substrate. The cost of the support structures is much lower than other processes, such as thermal compression bonding, to reduce the effect of bowing of dies and substrates on 3DIC formation. The support structures improves yield of 3DIC structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.