Methods of fabrication and testing of three-dimensional stacked integrated circuit system-in-package
US9570429B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2015 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Apr 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06541
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method of fabricating a 3D stacked IC SiP which includes: providing a first semiconductor wafer having a plurality of first dies formed thereon, each having a first wire bond pad and a first dielectric layer, at least a portion of the first wire bond pad is not covered by the first dielectric layer and constitutes an exposed area of the first die; providing a plurality of second dies, each having a second wire bond pad and a second dielectric layer, at least a portion of the second wire bond pad is not covered by the second dielectric layer and constitutes an exposed area of the second die different in size from that of the first die; aligning the second dies with the first dies and bonding the second dielectric layer to the first dielectric layer; plating the first semiconductor wafer bonded with the second dies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.