Patent · US Active

Semiconductor structure and recess formation etch technique

US9570600B2 · kind B2 · utility

14Cited by
7References
45Claims
0Family size

Assignee

Inventors

Key dates

Filing dateNov 15, 2013
Grant dateFeb 14, 2017
Priority date—
Expiry dateNov 15, 2033

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D64/256
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A semiconductor structure has a first layer that includes a first semiconductor material and a second layer that includes a second semiconductor material. The first semiconductor material is selectively etchable over the second semiconductor material using a first etching process. The first layer is disposed over the second layer. A recess is disposed at least in the first layer. Also described is a method of forming a semiconductor structure that includes a recess. The method includes etching a region in a first layer using a first etching process. The first layer includes a first semiconductor material. The first etching process stops at a second layer beneath the first layer. The second layer includes a second semiconductor material.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.