Clock gating for system-on-chip elements
US9571341B1 · kind B1 · utility
34Cited by
29References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2014 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Jun 29, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An aspect of the present disclosure provides a hardware element in a Network on Chip (NoC), wherein the hardware element includes a clock gating circuit configures one or more neighboring hardware elements to activate before receiving new incoming data and to sleep after a defined number of cycles, wherein the defined number of cycles can be counted from a cycle having non-receipt of incoming data and/or having a clearance of all data within an input queue of a source hardware element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.