Multi-stage interconnect network in a parallel processing network device
US9571380B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2014 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Feb 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/505
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A packet is received at a packet processing element, among a plurality of like packet processing elements, of a network device, and request specifying a processing operation to be performed with respect to the packet by an accelerator engine functionally different from the plurality of like packet processing elements is generated by the packet processing element. The request is transmitted to an interconnect network that includes a plurality of interconnect units arranged in stages. A path through the interconnect network is selected among a plurality of candidate paths, wherein no path of the candidate paths includes multiple interconnect units within a same stage of the interconnect network. The request is then transmitted via the determined path to a particular accelerator engine among multiple candidate accelerator engines configured to perform the processing operation. The processing operation is then performed by the particular accelerator engine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.