Patent · US Active

Testing stacked devices

US9575117B2 · kind B2 · utility

0Cited by

2References

15Claims

0Family size

Assignee

ADVANTEST CORPORATION · JP

Inventors

Ling Qi · Shanghai, CN
Tung Sheng Hsieh · San Jose, US

Key dates

Filing date	Apr 18, 2013
Grant date	Feb 21, 2017
Priority date	—
Expiry date	May 5, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/2893
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

Testing stacked devices. In accordance with a first method embodiment, a primary circuit assembly is accessed from a first circuit assembly carrier. The primary circuit assembly is placed into a test fixture. A secondary circuit assembly is accessed from a second circuit assembly carrier. The secondary circuit assembly is placed into the test fixture on top of the primary circuit assembly. The primary circuit assembly is tested in conjunction with said secondary circuit assembly while coupled together.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.