Replica path timing adjustment and normalization for adaptive voltage and frequency scaling
US9575553B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2014 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Apr 27, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor employs a set of replica paths at a processor to determine an operating frequency and voltage for the processor. The replica paths each represent one or more circuit paths at a functional module of the processor. The delays at the replica paths are normalized to increase the likelihood that the replica paths accurately represent the behavior of the circuit paths of the functional module. After normalization, a distribution of delay values is generated by varying, at each replica path, the delay at an output node of the replica path until a mismatch is detected between a signal at the output node of the replica path and the delayed representation of the signal. The resulting distribution of delay values can then be adjusted based on variations in reference voltages at the replica paths to account for potential distribution errors resulting from the reference voltage variations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.