Multi-device memory serial architecture
US9575662B2 · kind B2 · utility
0Cited by
4References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2015 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Mar 27, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Subject matter disclosed herein relates to memory devices comprising a memory array, a first port to interface with a memory controller directly or indirectly via another memory device, a second port to interface with yet another memory device, and a switch to selectively electrically connect the memory controller to a circuit path leading to the second port or to the memory array, wherein the switch may be responsive to a signal generated by the memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.