Cache control device having fault-tolerant function and method of operating the same
US9575692B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2015 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Jun 18, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The cache control device having the fault-tolerant function includes a cache memory configured to store first data with respect to a specific address read from a main memory, and generate and store a first parity bit corresponding to the first data, a shadow cache memory configured to store second data with respect to the specific address, and generate and store a second parity bit corresponding to the second data, and a fault detector configured to perform a parity check operation on the data of the specific address and the parity bit stored in at least one of the cache memory and the shadow cache memory when receiving a data read request with respect to the specific address from a processor, and transmit the data stored in a non-erroneous memory to the processor according to a result of the parity check operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.