Zero cycle move
US9575754B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2012 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Aug 9, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/384
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for reducing the latency of data move operations. A register rename unit within a processor determines whether a decoded move instruction is eligible for a zero cycle move operation. If so, control logic assigns a physical register identifier associated with a source operand of the move instruction to the destination operand of the move instruction. Additionally, the register rename unit marks the given move instruction to prevent it from proceeding in the processor pipeline. Further maintenance of the particular physical register identifier may be done by the register rename unit during commit of the given move instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.