Patent · US Active

Temporary pipeline marking for processor error workarounds

US9575836B2 · kind B2 · utility

0Cited by

2References

1Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Erez Barak · Hod HaSharon, IL
Steven R. Carlough · Poughkeepsie, US
Eyal Gonen · Nofit, IL
Juergen Haess · Schenefeld, DE
Silvia M. Mueller · Altdorf, DE

Key dates

Filing date	Aug 30, 2016
Grant date	Feb 21, 2017
Priority date	—
Expiry date	Aug 30, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F2201/86
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments include a computer system for temporary pipeline marking for processor error workarounds, the computer system having a processor configured to perform a method. The method includes monitoring a pipeline of the processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.