Failure recovery apparatus of digital logic circuit and method thereof
US9575852B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 24, 2015 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Jul 10, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1658
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Exemplary embodiments of the present invention relate to a failure recovery apparatus of digital logic circuit and method thereof when a fault occurs in the digital logic circuit. A failure recovery apparatus according to an embodiment of the present invention comprises: a fault detection block configured to determine fault occurrence by comparing output results of a plurality of digital logic circuit which perform the same operation using a clock having a first cycle; and a failure recovery block configured to perform a failure recovery operation of the plurality of digital logic circuit by using a clock having a second cycle which is longer than the first cycle when it is determined as that a fault occurs. According to exemplary embodiments of the present invention, when a fault occurs in digital logic circuits due to external factors, it provides high reliability in failure recovery of the digital logic circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.