Configurable cell design using capacitive coupling for enhanced timing closure
US9576101B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2015 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Mar 13, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/396
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for achieving clock timing closure in an integrated circuit (IC) design includes designing an IC using one or more component cells selected from a cell library to produce the design. A timing analysis of the design is performed to determine if timing constraints are satisfied. When a given time constraint is not satisfied, a component cell selected from the cell library is replaced with a replacement cell that has the same function and the same footprint as the replaced component cell, but has a different timing characteristic based on the phase relationship of the signal being capacitively coupled to enhance the likelihood of meeting the given time constraint. The timing analysis is repeated with the replacement cell. The process of replacing component cells and performing timing analysis may be iterative.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.