Three dimensional semiconductor memory device
US9576664B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2013 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Dec 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device may include a string including at least one drain select transistor, a plurality of first memory cells, a first connection element, a plurality of second memory cells, a second connection element, a plurality of third memory cells, and at least one source select transistor, wherein the at least one drain select transistor, the plurality of first memory cells, the plurality of second memory cells, the plurality of third memory cells, and the at least one source select transistor connected serially via the first connection element and the second connection element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.