Fan-out wafer level packaging and manufacturing method thereof
US9576933B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 6, 2016 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Jan 6, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fan-out wafer-level-package (FOWLP) is provided. The FOWLP includes a redistribution layer (RDL) comprising a dielectric layer and a first metal layer; a passive device in the first metal layer; a first passivation layer covering a top surface of the RDL; a second passivation layer covering a bottom surface of the RDL; a chip mounted on the first passivation layer; a molding compound around the chip and on the first passivation layer; a via opening penetrating through the second passivation layer, the dielectric layer, and the second passivation layer, thereby exposing a terminal of the chip; a contact opening in the second passivation layer; and a second metal layer in the via opening and the contact opening to electrically connect one electrode of the passive device with the terminal of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.