Yi-Jen Lo
23Patents
2h-index
11Co-inventors
50Inventor score
Filing activity: Dec 7, 2005 → Oct 23, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9576933B1 | Fan-out wafer level packaging and manufacturing method thereof | Electricity | 3 | Active |
| US10818508B2 | Semiconductor structure and method for preparing the same | Electricity | 2 | Active |
| US9543270B1 | Multi-device package and manufacturing method thereof | Electricity | 2 | Active |
| US9748106B2 | Method for fabricating semiconductor package | Electricity | 1 | Active |
| US10593637B2 | Multi-device packages and related microelectronic devices | Electricity | 1 | Active |
| US7341950B2 | Method for controlling a thickness of a first layer and method for adjusting the thickness of different first layers | Electricity | 1 | Expired |
| US11842979B2 | Semiconductor device and method of manufacturing the same | Electricity | 1 | Active |
| US12266622B2 | Method of manufacturing semiconductor structure having hybrid bonding pad | Electricity | 0 | Active |
| US12400951B2 | Semiconductor device and method of manufacturing the same | Electricity | 0 | Active |
| US12278211B2 | Manufacturing method of semiconductor device | Electricity | 0 | Active |
| US10373922B2 | Methods of manufacturing a multi-device package | Electricity | 0 | Active |
| US11631656B2 | Method for manufacturing semiconductor structure | Electricity | 0 | Active |
| US10811382B1 | Method of manufacturing semiconductor device | Electricity | 0 | Active |
| US11482474B2 | Forming a self-aligned TSV with narrow opening in horizontal isolation layer interfacing substrate | Electricity | 0 | Active |
| US12295137B2 | Method of manufacturing tsemiconductor device having bonding structure | Electricity | 0 | Active |
| US8003528B2 | Semiconductor structure and method for making the same | Electricity | 0 | Active |
| US12293982B2 | Semiconductor structure having hybrid bonding pad | Electricity | 0 | Active |
| US11488840B2 | Wafer-to-wafer interconnection structure and method of manufacturing the same | Electricity | 0 | Active |
| US11610878B1 | Semiconductor device with stacked chips and method for fabricating the same | Electricity | 0 | Active |
| US10679958B2 | Methods of manufacturing a multi-device package | Electricity | 0 | Active |
| US11211351B2 | Apparatuses including redistribution layers and related microelectronic devices | Electricity | 0 | Active |
| US11342307B2 | Semiconductor structure and manufacturing method thereof | Electricity | 0 | Active |
| US11876077B2 | Semiconductor device and method of manufacturing the same | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.