RRAM cell with PMOS access transistor
US9577009B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2015 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Nov 13, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to an integrated chip comprising an RRAM cell that is driven by a PMOS transistor, and an associated method of formation. In some embodiments, the integrated chip has a PMOS transistor arranged within a semiconductor substrate. A resistive RRAM cell is arranged within an inter-level dielectric (ILD) layer overlying the semiconductor substrate. The RRAM cell has a first conductive electrode separated from a second conductive electrode by a dielectric data storage layer having a variable resistance. The first conductive electrode is connected to a drain terminal of the PMOS transistor by one or more metal interconnect layers. The use of a PMOS transistor to drive the RRAM cell allows for impact of the body effect to be reduced and therefore allows for a reset operation to be performed at a low power and in a short amount of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.