Transistor structure with reduced parasitic side wall characteristics

US9577039B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventor

• Hubert Rothleitner · Villach, AT

Key dates

• Filing date: Dec 30, 2014
• Grant date: Feb 21, 2017
• Expiry date: Dec 30, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/663

Abstract

A MOS transistor structure for matched operation in weak-inversion or sub-threshold range (e.g. input-pair of operational amplifier, comparator, and/or current-mirror) is disclosed. The transistor structure may include a well region of any impurity type in a substrate (SOI is included). The well-region can even be represented by the substrate itself. At least one transistor is located in the well region, whereby the active channel-region of the transistor is independent from lateral isolation interfaces between GOX (gate oxide) and FOX (field oxide; including STI-shallow trench isolation).