Method of fabricating semiconductor MOS device
US9577069B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2016 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Apr 24, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0281
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a MOS device is disclosed. A substrate having an active area (AA) silicon portion and shallow trench isolation (STI) region surrounding the active area is provided. A hard mask is formed on the substrate. A portion of the hard mask is removed to form an opening on the AA silicon portion. The opening exposes an edge of the STI region. The AA silicon portion is recessed through the opening to a predetermined depth to form a silicon spacer along a sidewall of the STI region in a self-aligned manner. An oxidation process is performed to oxidize the AA silicon portion and the silicon spacer to form a gate oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.