RRAM cell bottom electrode formation
US9577191B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2014 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Feb 27, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a reduced leakage current, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode over a lower metal interconnect layer using an atomic layer deposition (ALD) process to form at least a top portion of the bottom electrode. A dielectric data storage layer is formed onto the top portion of the bottom electrode in-situ with forming the top portion of the bottom electrode. A top electrode is formed over the dielectric data storage layer, and an upper metal interconnect layer is formed over the top electrode. By forming the top portion of the bottom electrode using an ALD process that is in-situ with the formation of the overlying dielectric data storage layer, leakage current, leakage current distribution and device yield of the RRAM cell are improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.