Methods and circuits for testing partial circuit designs
US9581643B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2015 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | Oct 27, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3308
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and circuits are disclosed for testing a partial circuit design including circuit modules having a set of ports configured to be driven by signals from ports of one or more circuits omitted from the partial circuit. The set of ports are identified by identifying ports that are not connected by a net to another port or input/output (I/O) pin in the circuit design and that form inputs to slave circuits in the circuit modules. A traffic generator circuit is added to the partial design to form a test circuit design. The traffic generator circuit is configured to provide to the set of ports respective input data signals having a pattern consistent with master-to-slave communication. Operation of a test circuit design is modeled. A set of data signals generated by the circuit modules during the modeled operation of the test circuit design is captured and stored.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.