Selecting I/O interrupt target for multi-core server systems
US9582346B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2013 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | Sep 27, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0793
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Implementations of the present disclosure involve a system and/or method for handling errors in a multi-node commercial computing system running a number of guest applications simultaneously. In particular, the system and/or method provides the ability to program on a per-error basis the destination within the system for an interrupt based on an I/O error, the ability to provision for multiple/redundant error reporting paths for a class of more severe errors and/or distributed set of error status and log registers to aid software in narrowing down the source of an error that triggered the interrupt. In addition, the system provides for dynamically altering the destination of the error handling in response to one or more operating conditions of the system. Such flexibility in the system provides for a more robust error handling without impacting the performance of the multi-node computing system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.