Instruction and logic for support of code modification in translation lookaside buffers
US9582432B2 · kind B2 · utility
3Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2016 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | Jun 9, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/68
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a core with logic to execute a translated instruction. The translated instruction is translated from an instruction stored in a memory location. The processor further includes a translation lookaside buffer including logic to store translation indicators from a physical map. Each translation indicator indicates whether a corresponding memory location includes translated code to be protected. The processor further includes a translation indicator agent including logic to determine whether the buffer indicates whether the memory location has been modified subsequent to translation of the instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.