Loop structure for operations in memory
US9583163B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2016 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | Feb 2, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example apparatus might also include a controller configured to cause sensing circuitry to iterate through a plurality of first elements and a plurality of second elements via a loop structure to perform an operation using the plurality of first elements and the plurality of second elements, wherein a conditional statement associated with the loop structure is used to determine whether at least one of a plurality of bits stored as an iterator mask has a particular bit-value. An example apparatus might also include sensing circuitry controllable to perform a shift operation using the iterator mask at each iteration of the loop structure and perform an AND operation using the iterator mask at each iteration of the loop structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.