SRAM read preferred bit cell with write assist circuit
US9583178B2 · kind B2 · utility
12Cited by
8References
18Claims
0Family size
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Key dates
| Filing date | Jan 15, 2013 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | Oct 16, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for static memory cells. A static memory cell may include a first pass gate transistor including a first back gate node and a second pass gate transistor including a second back gate node. The static memory cell may include a first pull down transistor including a third back gate node and a second pull down transistor including a fourth back gate node. The source node of the first pull down transistor, source node of the second pull down transistor, and first, second, third, and fourth back gate nodes are electrically coupled to each other to form a common node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.