SRAM device capable of working in multiple low voltages without loss of performance
US9583181B1 · kind B1 · utility
2Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2015 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | Oct 1, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device comprises a tracking control circuit for controlling the write operation or the read operation of the memory device. The tracking control circuit comprises a plurality of tracking cells, wherein the timing characteristics of the tracking cells emulate the timing characteristics of a bit cell during a write operation or a read operation of the memory device. The memory device further comprises at least two reference word lines for configuring the number of tracking cells of the tracking control circuit; and a selection circuit configured to activate one or more of the at least two reference word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.