Semiconductor memory device and testing method thereof
US9583215B2 · kind B2 · utility
4Cited by
9References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2014 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | Nov 25, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device is provided which includes memory cells, a first error correction code (ECC) circuit configured to generate at least one selected parity bit corresponding to a selected data bit using an error correction code during a write operation and to correct an error of the selected data bit using the selected parity bit during a read operation, and a test circuit configured to selectively perform at least one of an error correction operation and a redundancy repair operation on at least one of the selected data bit and the selected parity bit based on test mode register set (TMRS) information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.