Processes and apparatus for preparing heterostructures with reduced strain by radial compression

US9583364B2 · kind B2 · utility

Assignee

• SunEdison Semiconductor Limited (UEN201334164H) · SG

Inventors

• Robert J. Falster · London, GB
• Vladimir V. Voronkov · Albino, IT
• John A. Pitney · Saint Peters, US
• Peter Albrecht · Hamburg, DE

Key dates

• Filing date: Dec 27, 2013
• Grant date: Feb 28, 2017
• Expiry date: Jan 9, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/6875
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.