Systems and methods for high-speed, low-profile memory packages and pinout designs
US9583452B2 · kind B2 · utility
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5References
17Claims
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Key dates
| Filing date | Sep 15, 2016 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | Sep 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.