Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow

US9583488B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Younsung Choi · Plano, US
• Steven Lee Prins · Fairview, US

Key dates

• Filing date: Dec 19, 2014
• Grant date: Feb 28, 2017
• Expiry date: Dec 19, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/10

Abstract

An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and with PMOS transistors with gate overhang of active that are not longer than the minimum design rule.