CMOS nanowire structure

US9583491B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Seiyon Kim · Portland, US
• Kelin J. Kuhn · Beaverton, US
• Tahir Ghani · Portland, US
• Anand S. Murthy · Beaverton, US
• Annalisa Cappellani · Portland, US
• Stephen M. Cea · Hillsboro, US
• Rafael Rios · Portland, US
• Glenn A. Glass · Portland, US

Key dates

• Filing date: Nov 20, 2015
• Grant date: Feb 28, 2017
• Expiry date: Nov 20, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6212
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.