Apparatus and method for integrated circuit bit line sharing
US9583494B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Oct 23, 2013 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | Oct 23, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array includes a first memory column having a first bit line, a first word line and a second bit line. The memory array also includes a second memory column having the second bit line, a second word line and a third bit line. The first memory column and the second memory column are configured to share the second bit line. The sharing of the second bit line facilitates sharing one or more memory array components between the first memory column and the second memory column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.