Si recess method in HKMG replacement gate technology

US9583591B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Harry-Hak-Lay Chuang · Austin, US
• Wei-Cheng Wu · Hengshan, TW
• Chin-Yi Huang · Fremont, US
• Shih-Chang Liu · Guanmiao, TW
• Chang-Ming Wu · New Taipei, TW

Key dates

• Filing date: Mar 14, 2014
• Grant date: Feb 28, 2017
• Expiry date: May 12, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017

Abstract

The present disclosure relates to a method of embedding an ESF3 memory in a HKMG integrated circuit that utilizes a replacement gate technology. The ESF3 memory is formed over a recessed substrate which prevents damage of the memory control gates during the CMP process performed on the ILD layer. An asymmetric isolation zone is also formed in the transition region between the memory cell and the periphery circuit boundary.