Vertical transistor and local interconnect structure
US9583615B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2015 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | Feb 17, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
Abstract
A first patterned stack and a second patterned stack are formed over a substrate, each of which includes a bottom semiconductor layer, a bottom dielectric spacer layer, a conductive material layer, and a top dielectric spacer layer. Gate dielectrics and vertical semiconductor portions are sequentially formed on each patterned stack. Vertical semiconductor portions are removed from around the second patterned stack, while masked around the first patterned stack. Electrical dopants are introduced to top regions and bottom regions of the remaining vertical semiconductor portions to form a vertical switching device that includes the first patterned stack, while the second patterned stack functions as a horizontal interconnect structure. The vertical switching device can be a transistor or a gated diode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.