Partial reconfiguration control interface for integrated circuits
US9584130B1 · kind B1 · utility
16Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 25, 2016 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | May 25, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for coordinating the partial reconfiguration of a region of a configurable device (e.g., a SDM/CNoC/LSM system or device) through an interface that coordinates the stopping of the current persona in that region, the resetting of the new current persona, and the starting of the new persona in a manner that does not corrupt the memory of the affected region. The interface further provides signaling that the static region can use to protect itself during the partial reconfiguration, and disallows multiple partial reconfigurations of the same region at the same time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.