Asynchronous clock generation for time-interleaved successive approximation analog to digital converters
US9584144B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2016 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | Apr 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generator includes: a first input to receive a global clock signal; a second input to receive a completion signal; a third input to receive differential outputs in a conversion cycle from a comparator; and a logic circuit configured to generate a control clock signal based at least in part on the global clock signal and the differential outputs, and to provide the control clock signal to the comparator for a next conversion cycle; and wherein the logic circuit is also configured to disable the control clock signal in response to the completion signal indicating a completion of required conversion cycles in a conversion phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.