Optimizing generation of test configurations for built-in self-testing
US9588177B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2016 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Jan 5, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3187
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Technical solutions are described for optimizing a set of test configurations used for testing an electronic circuit that includes latches. An example method includes receiving a test configuration that includes settings that initiate a set of predetermined input values and corresponding expected output values. The method also includes evaluating the test configuration by executing the electronic circuit according to the test configuration and recording parametric data during the execution, where the parametric data is representative of switching activity of the latches in the electronic circuit. The evaluation includes analyzing the parametric data to identify presence of a predetermined pattern in the switching activity and selecting the test configuration based on the predetermined pattern being absent/present in the switching activity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.