Partitioning memory in programmable integrated circuits
US9589088B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2015 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Jun 22, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various example implementations are directed to circuits and methods for partitioning a memory for a circuit design in a programmable IC. A user interface is provided for a user to define subsystems, master circuits, memory segments, and permissions for accessing the memory segments by the master circuits. For each defined memory segment, a respective access control entry is generated that includes data for determining master circuits that are permitted access to the memory segment by the user-defined permissions. A first portion of configuration data is generated that is configured to cause a memory management circuit in the programmable IC to enforce access to address ranges, corresponding to the respective memory segments, in a memory of the programmable IC according to the respective access control entries. A second portion of configuration data is generated that is configured to cause programmable resources of the programmable IC to implement the circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.