Method of forming finFET gate oxide
US9589804B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jul 30, 2015 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Jul 30, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6211
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top surface, a first side surface adjacent to the top surface, and a second side surface which is disposed under and adjacent to the first side surface. The lining oxide layer peripherally encloses the second side surface of the semiconductor fin. The silicon nitride based layer is disposed conformal to the lining oxide layer. The gate oxide layer is disposed conformal to the top surface and the first side surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.