FinFET spacer etch with no fin recess and no gate-spacer pull-down
US9589811B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 24, 2015 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Jun 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method may include providing a patterned feature extending from a substrate plane of a substrate, the patterned feature including a semiconductor portion and a coating in an unhardened state extending along a top region and along sidewall regions of the semiconductor portion; implanting first ions into the coating, the first ions having a first trajectory along a perpendicular to the substrate plane, wherein the first ions form a etch-hardened portion comprising a hardened state disposed along the top region; and directing a reactive etch using second ions at the coating, the second ions having a second trajectory forming a non-zero angle with respect to the perpendicular, wherein the reactive etch removes the etch-hardened portion at a first etch rate, wherein the first etch rate is less than a second etch rate when the second ions are directed in the reactive etch to the top portion in the unhardened state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.