Semiconductor arrangement, method for producing a number of chip assemblies and method for producing a semiconductor arrangement

US9589859B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Gottfried Beer · Nittendorf, DE
• Edward Fuergut · Nuremberg, DE
• Juergen Hoegerl · Regensburg, DE
• Olaf Hohlfeld · Warstein, DE
• Peter Kanschat · Soest, DE

Key dates

• Filing date: Aug 19, 2014
• Grant date: Mar 7, 2017
• Expiry date: Sep 29, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/13091
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor arrangement includes a plurality of chip assemblies, each of which includes a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally circumferentially in a ring-shaped fashion such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.