Whole wafer edge seal
US9589895B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2015 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Apr 16, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/564
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates generally to semiconductor devices and more particularly, to a structure and method of creating a non-permeable edge seal around a whole wafer. The edge seal may be located between an inner region of a wafer comprising product chips and an outer edge of the wafer. The edge seal may comprise a fillet region adjacent the inner region, and a dielectric extension adjacent the fillet region. The dielectric extension region may be impermeable to moisture and composed of a dielectric layer on the wafer and a capping layer on the dielectric layer. The fillet region may comprise a lower metal fillet directly on the wafer, a dielectric layer on the lower metal fillet, an upper metal fillet on the dielectric layer, and a capping layer on the upper metal fillet. The fillet region may be adjacent to and in contact with a permeable layer formed on the product region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.