Semiconductor device having a gate cutting region and a cross-coupling pattern between gate structures
US9589899B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2015 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Jul 17, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor device, a first gate structure having a first end portion is formed on a substrate. A second gate structure is formed on the substrate, and has a second end portion opposite to the first end portion of the first gate structure in a diagonal direction. A cross-coupling pattern is formed between the first and second gate structure, and electrically connects the first and second gate structures to each other. A first contact plug directly contacts an upper portion of the first end portion of the first gate structure and a first upper sidewall of the cross-coupling pattern. A second contact plug directly contacts an upper portion of the second end portion of the second gate structure and a second upper sidewall of the cross-coupling pattern. In the semiconductor device, a parasitic capacitance due to the cross-coupling structure may decrease.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.