Flip chip stacking utilizing interposer
US9589913B1 · kind B1 · utility
2Cited by
2References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2013 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Nov 19, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/37001
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interposer and a method for stacking dies utilizing such an interposer in an integrated circuit are disclosed. The interposer includes a substrate and a plurality of vias defined in the substrate. At least one of the plurality of vias of the interposer is positioned to establish a connection with at least one of the plurality of vias of a first die. At least one additional die is positioned to establish a connection with the first die utilizing the connection established between the interposer and the first die through at least one of the vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.