Semiconductor package having stacked semiconductor chips
US9589945B2 · kind B2 · utility
12Cited by
10References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2015 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Jul 21, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16195
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a package base substrate, at least one first semiconductor chip disposed on the package base substrate, and at least one stacked semiconductor chip structure disposed on the package base substrate adjacent to the at least one first semiconductor chip. The at least one stacked semiconductor chip includes a plurality of second semiconductor chips. A penetrating electrode region including a plurality of penetrating electrodes is disposed adjacent to an edge of the at least one stacked semiconductor chip structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.