Structure and method of operation for improved gate capacity for 3D NOR flash memory
US9589982B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2015 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Sep 15, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention provide improved three-dimensional memory cells, arrays, devices, and/or the like and associated methods. In one embodiment, a three-dimensional memory cell is provided. The three-dimensional memory cell comprises a first conductive layer; a third conductive layer spaced apart from the first conductive layer; a channel conductive layer connecting the first conductive layer and the third conductive layer to form an opening having internal surfaces; a dielectric layer disposed along the internal surfaces of the opening surrounded by the first conductive layer, the channel conductive layer and the third conductive layer; and a second conductive layer interposed and substantially filling a remaining open portion formed by the dielectric layer. The first conductive layer, the dielectric layer, and the second conductive layer are configured to form a staircase structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.