Methodology and structure for field plate design
US9590053B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2015 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Jan 26, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/378
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a high voltage transistor device having a field plate, and a method of formation. In some embodiments, the high voltage transistor device has a gate electrode disposed over a substrate between a source region and a drain region located within the substrate. A dielectric layer laterally extends from over the gate electrode to a drift region arranged between the gate electrode and the drain region. A field plate is located within a first inter-level dielectric layer overlying the substrate. The field plate laterally extends from over the gate electrode to over the drift region and vertically extends from the dielectric layer to a top surface of the first ILD layer. A plurality of metal contacts, having a same material as the field plate, vertically extend from a bottom surface of the first ILD layer to a top surface of the first ILD layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.