Receiving circuit, semiconductor apparatus and system using the same
US9590596B1 · kind B1 · utility
8Cited by
3References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 6, 2016 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Apr 6, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0292
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiving circuit may include a wide range receiving circuit and a parallelizing circuit. The wide range receiving circuit may amplify an input signal which swings within a first range and generate an intermediate output signal which swings within a second range wider than the first range. The parallelizing circuit may compare the intermediate output signal with a second reference voltage and amplify the intermediate output signal accordingly and generate output signals which swing within a third range wider than the second range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.